Parametric reliability analysis of no-underfill flip chip package

IEEE Transactions on Components and Packaging Technologies

Volumn 24, Issue 4, 2001, Pages 635-640

  Chiang, Kuo Ning ^a   Liu, Zheng Nan ^a   Peng, Chih Tang ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Ceramic like; Constraint layer; CTE; Flip chip; Parametric analysis; Reliability; Reworkability; Underfill

Indexed keywords

FLIP CHIP DEVICES; RELIABILITY THEORY; SEMICONDUCTING SILICON; SOLDERED JOINTS; SUBSTRATES; SURFACE MOUNT TECHNOLOGY; THERMAL EXPANSION;

FLIP CHIP PACKAGES;

CHIP SCALE PACKAGES;

EID: 0035691474     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/6144.974953     Document Type: Article

References (14)

1. Reliability of flip chip on board assemblies
2. Impact of underfill filler particles on reliability of flip-chip interconnects
3. The effect of underfill and underfill delamination on the thermal stress in flip-chip solder joints
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5. Potential failure sites in a flip-chip package with and without underfill
6. Parametric finite element analysis of flip chip reliability
7. Measurements of mechanical behavior of high lead lead-tin solder joints subjected to thermal cycling
8. Parametric analysis of thermally enhanced BGA reliability using a finite-volume-weighted averaging technique
9. Large-scaled 3-D area array electronic packaging analysis
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12. On enhancing eutectic solder joint reliability using a second-reflow-process approach
13. A study of the effects of cyclic thermal stresses on a ductile metal
14. Mechanics