High-throughput high-density mapping and spectrum analysis of transistor gate length variations in SRAM circuits

IEEE Transactions on Semiconductor Manufacturing

Volumn 14, Issue 4, 2001, Pages 318-329

  Ouyang, Xu ^a,b,c   Deeter, Tim ^d   Berglund, C Neil ^a,b,e   Pease, R Fabian W ^a,b   Lee, Jesse ^d   McCord, Mark A ^b,f  

^a IEEE   (United States)

^b Stanford University   (United States)

^c PDF SOLUTIONS INC   (United States)

^d INTEL CORPORATION   (United States)

^e OREGON HEALTH AND SCIENCE UNIVERSITY   (United States)

^f KLA TENCOR CORPORATION   (United States)

Author keywords

Active electrical metrology; CD; Inter transistor; Lithography; Metrology; Short range; Spatial frequency; Spatial variations; SRAM

Indexed keywords

HIGH-THROUGHPUT HIGH-DENSITY MAPPING; LAYOUT-DEPENDENT PERIODIC ERROR; STATIC RANDOM ACCESS MEMORY; TRANSISTOR GATE LENGTH;

COMPUTER SIMULATION; ELECTRIC CURRENT MEASUREMENT; INTEGRATED CIRCUITS; LITHOGRAPHY; RANDOM ACCESS STORAGE; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE MANUFACTURE; SPECTRUM ANALYSIS;

GATES (TRANSISTOR);

EID: 0035508266     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.964319     Document Type: Article

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