A low jitter 125-1250MHz process independent 0.18μm CMOS PLL based on a sample-reset loop filter

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 394-395

  Maxim, A ^a   Scott, B ^a   Schneider, E ^a   Hagge, M ^a   Chacko, S ^a   Stiurca, D ^a  

^a Cirrus Logic   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CAPACITANCE; CMOS INTEGRATED CIRCUITS; GAIN CONTROL; JITTER; NAND CIRCUITS; NATURAL FREQUENCIES; OSCILLATORS (ELECTRONIC);

LOOP FILTERS; PHASE DETECTOR FREQUENCY SPURS; POWER-SUPPLY-REJECTION RATIOS (PSRR);

PHASE LOCKED LOOPS;

EID: 0035058239     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. Low jitter process independent DLL and PLL based on self-biased techniques
2. Cell based fully integrated CMOS frequency synthesizer