An adaptive path selection method for delay testing

IEEE Transactions on Instrumentation and Measurement

Volumn 50, Issue 5, 2001, Pages 1109-1118

  Jone, Wen Ben ^a,b   Yeh, Wu Sung ^c   Yeh, Chingwei ^d   Das, Sunil R ^a,e  

^a IEEE   (United States)

^b 705 Engineering Research Center   (United States)

^c INSTITUTE FOR INFORMATION INDUSTRY   (Taiwan)

^d NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^e UNIVERSITY OF OTTAWA   (Canada)

Author keywords

Delay testing; Long path selection; New path construction; Path delay fault model; Path segmentation

Indexed keywords

ADAPTIVE PATH SELECTION METHOD; CIRCUIT UNDER TEST; DELAY TESTING; LONG PATH SELECTION; NEW PATH CONSTRUCTION; PATH DELAY FAULT MODEL; PATH SEGMENTATION;

ALGORITHMS; C (PROGRAMMING LANGUAGE); COMPUTER SIMULATION; FAILURE ANALYSIS; LOGIC CIRCUITS; LOGIC GATES;

INTEGRATED CIRCUIT TESTING;

EID: 0035483769     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/19.963168     Document Type: Article

References (10)

1. Efficient test coverage determination for delay faults
2. Model for delay faults based upon paths
3. Path sensitization in critical path problem
4. On path selection in combinational logic circuits
5. Delay testing for nonrobust untestable circuits
6. Effective path selection for delay fault testing of sequential circuits
7. Classification and test generation for path delay faults using single stuck fault tests
8. On the general false path problem in timing analysis
9. Generation of high quality tests for robustly untestable path delay faults
10. Segment delay faults: A new fault model