On effective I DDQ testing of low-voltage CMOS circuits using leakage control techniques

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 5, 2001, Pages 718-725

  Chen, Zhanping ^a,b   Wei, Liqiong ^a,b   Roy, Kaushik ^a,c  

^a IEEE   (United States)

^b INTEL CORPORATION   (United States)

^c PURDUE UNIVERSITY   (United States)

Author keywords

CMOS; Low voltage; Low power dissipation; Power consumption; Reliability; Test; VLSI

Indexed keywords

LEAKAGE CONTROL TECHNIQUES;

ELECTRIC POTENTIAL; ENERGY DISSIPATION; LEAKAGE CURRENTS; RELIABILITY; THRESHOLD LOGIC; VLSI CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0035472595     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.953504     Document Type: Article

References (30)

1. DDQ testing of deep submicron CMOS ICs
2. DDQ testing of bridging faults in CMOS circuits
3. Low-power CMOS digital design
4. Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks
5. CMOS scaling for high performance and low power-The next ten years
6. E-PROOFS: A CMOS bridging fault simulator
7. A gate-level leakage power reduction method for ultra-low-power CMOS circuits
8. DDQ test and diagnosis of CMOS circuits
9. Accurate CMOS bridging fault simulation
10. DDQ testing
11. Models and algorithms for bounds on leakage in CMOS circuits
12. Transistor sizing issues and tool for multi-threshold CMOS technology
13. Intrinsic leakage in low power deep submicron CMOS ICs
14. Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits
15. Enhancement of resolution in supply current based testing for large ICs
16. Design of IC's applying built-in current testing
17. Current ratios: A self-scaling technique for production IDDQ testing
18. Fast and accurate CMOS bridging fault simulation
19. DDQ testing for signal and bias paths in CMOS IC's for defect diagnosis
20. BSIM: Berkeley short-channel IGFET model for MOS transistors
21. A 1-V high-speed MTCMOS circuit scheme for power-down applications
22. DDQ testing: Issues present and future
23. IC defects-based testability analysis
24. DDQ testing
25. A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
26. Design and optimization of dual threshold circuits for low voltage low power applications
27. Standby leakage reduction in high-performance circuits using transistor stack effects