Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 456-462

  Lee, Terry ^a   Hajj, Ibrahim N ^a   Rudnick, Elizabeth M ^a   Patel, Janak H ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; DATA STRUCTURES; ELECTRIC CURRENTS; ERROR DETECTION; FAILURE ANALYSIS; GENETIC ALGORITHMS; VLSI CIRCUITS;

AUTOMATIC TEST PATTERN GENERATOR; BENCHMARK CIRCUITS; BRIDGING FAULTS; CURRENT TESTING; GENETIC ALGORITHM BASED TEST GENERATION; TWO LINE BRIDGING FAULT SET;

INTEGRATED CIRCUIT TESTING;

EID: 0029713581     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)