Synthesize pass transistor logic gate by using free binary decision diagram

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 1997, Pages 201-205

  Tachibana, Masayoshi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; HEURISTIC METHODS;

FREE BINARY DECISION DIAGRAM (FDDD); PASS TRANSISTOR LOGIC GATES;

LOGIC GATES;

EID: 0030648539     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)