C5M - A control-logic layout synthesis system for high-performance microprocessors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 1, 1998, Pages 14-23

  Burns, Jeffrey L ^a,b,c   Feldman, Jack A ^a,b,c  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

^c IBM HAIFA RESEARCH LAB   (Israel)

Author keywords

Circuit synthesis, cmos integrated circuits, design automation, integrated circuit design, integrated circuit layout, layout, microprocessors, routing

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED LOGIC DESIGN; ELECTRIC NETWORK SYNTHESIS; MICROPROCESSOR CHIPS;

CONTROL LOGIC LAYOUT SYNTHESIS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0031704321     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.673629     Document Type: Article

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