Output buffer with self-adjusting slew rate and on-chip compensation

Proceedings - 1998 IEEE Symposium on IC/Package Design Integration, IPDI 1998

Volumn 1998-February, Issue , 1998, Pages 1-5

  Lim, Chee How ^a   Daasch, W Robert ^b  

^a INTEL CORPORATION   (United States)

^b Portland State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS;

COMPENSATION CONTROL; CURRENT DRIVES; ENVIRONMENTAL STRESS; MULTIPLE OUTPUTS; NOISE PERFORMANCE; SELF-ADJUSTING; SWITCHING CONDITIONS; TEMPERATURE VARIATION;

ELECTRIC NETWORK ANALYSIS;

EID: 85044580340     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDI.1998.663621     Document Type: Conference Paper

References (9)

1. Barry C. Johnson, "High Performance Integrated Circuit Packaging," Proceedings of 1988 Custom Integrated Circuit Conference, pp. 23.1.1-23.1.6, May 1988.
2. Howard Test, "Trends in Semiconductor Packaging, A Merchant House View," Proceedings of Custom Integrated Circuit Conference, pp. 23.2.1-23.2.3, May 1988.
3. Ichiro Tomioka, Masahiko Hyozo, and others, "Current Control Buffer for Multi Switching CMOS SOG," Proceedings of 1990 Custom Integrated Circuit Conference, pp. 11.7.1-11.7.4, May 1990.
4. Ernestina Chioffi, Franco Maloberti, and others, "High-Speed, Low-Switching Noise CMOS Memory Data Output Buffer," IEEE Journal of Solid-State Circuits, Vol. 29, No. 11, pp. 1359-1365, November 1994.
5. Thaddeus Gabara, Wilhlem Fischer, and others, "Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers," Proceedings of 1996 Custom Integrated Circuit Conference, pp.13.5.1-13.5.4, May 1996.
6. Kathushi Asahina, Shuichi Kato, and Shinpei Kayano, "Output Buffer with On-Chip Compensation Circuit," Proceedings of 1993 Custom Integrated Circuit Conference, pp. 29.1.1-29.1.4, May 1993.
7. Tomonori Sekiguchi, Masashi Horiguchi, and others, "Low-Noise, High-Speed Data Transmission Using a Ringing-Canceling Output Buffer," IEEE Journal of Solid-State Circuits, Vol. 30, No. 12, pp. 1569-1574, December 1995.
8. R. Senthinathan, and J. Prince, "Simultaneous Switching Ground Noise Calculation for Packaged CMOS Devices," IEEE Journal of Solid-State Circuits, Vol. 26, pp. 1724-1728, November 1991.
9. C.H. Lim, "High-Performance Input/Output Circuit for CMOS Integrated Circuit Interface," MSEE Thesis, Dept. of Electrical Engineering, Portland State University, July 1997.