Effects of simultaneous switching noise on the tapered buffer design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 5, Issue 3, 1997, Pages 290-300

  Vemuru, Srinivasa R ^a,b  

^a CITY UNIVERSITY OF NEW YORK   (United States)

^b IEEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC VARIABLES CONTROL; SWITCHING CIRCUITS; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

BUFFER PROPAGATION DELAY; PARASITIC INDUCTANCE; SIMULTANEOUS SWITCHING NOISE (SSN); SOFTWARE PACKAGE SPICE;

BUFFER CIRCUITS;

EID: 0031233443     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.609872     Document Type: Article

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