Self-aligned gate and source drain contacts in inverted-staggered a-Si:H thin-film transistors fabricated using selective area silicon PECVD

IEEE Electron Device Letters

Volumn 19, Issue 6, 1998, Pages 180-182

  Yang, C S ^a   Read, W W ^a   Arthur, C ^a   Srinivasan, E ^a   Parsons, G N ^a  

^a North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHOUS SILICON; CHEMICAL VAPOR DEPOSITION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CONTACTS; GATES (TRANSISTOR); PLASMA APPLICATIONS; REACTIVE ION ETCHING;

SELECTIVE AREA SILICON PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION;

THIN FILM TRANSISTORS;

EID: 0032095282     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.678536     Document Type: Article

References (7)

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