Functional vector generation for HDL models using linear programming and Boolean satisfiability

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 8, 2001, Pages 994-1002

  Fallah, Farzan ^a,b   Devadas, Srinivas ^a,c   Keutzer, Kurt ^a,d  

^a IEEE   (United States)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Boolean satisfiability; Functional vector generation; HDL; HSAT; Linear programming

Indexed keywords

DATA PATH MODULES; FUNCTIONAL VECTOR GENERATION; LOGIC EQUATIONS; STANDARD SATISFIABILITY;

ALGORITHMS; APPROXIMATION THEORY; BOOLEAN FUNCTIONS; COMPUTATIONAL METHODS; INTEGRATION; LINEAR PROGRAMMING; LOGIC GATES; MATHEMATICAL MODELS;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 0035424258     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.936380     Document Type: Article

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