Architecture validation for processors

ACM SIGARCH (Association for Computing Nachinery Special Interest Group on Computer Architecture) - Conference Proceedings

Volumn , Issue , 1995, Pages 404-413

  Ho, Richard C ^a   Yang, C Han ^a   Horowitz, Mark A ^a   Dill, David L ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; CONTROL SYSTEMS; ERROR COMPENSATION; LARGE SCALE SYSTEMS; LOGIC DESIGN; MULTIPROCESSING SYSTEMS; PERFORMANCE;

ARCHITECTURE VALIDATION; CONTROL LOGIC; ERROR-CAUSING INTERACTIONS; VERILOG DESCRIPTION;

MICROPROCESSOR CHIPS;

EID: 0029195606     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/223982.224450     Document Type: Conference Paper

References (13)