Reduction of power consumption in scan-based circuits during test application by an input control technique

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 7, 2001, Pages 911-917

  Huang, T C ^a   Lee, K J ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

ATPG; Full scan; Low power testing; Power minimization; VLSI testing

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; C (PROGRAMMING LANGUAGE); SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE TESTING; SEQUENTIAL CIRCUITS;

AUTOMATIC TEST PATTERN GENERATION; INPUT CONTROL TECHNIQUE; LATCH ORDERING TECHNIQUE; POWER CONSUMPTION; SCAN-BASED CIRCUITS; VECTOR ORDERING TECHNIQUE;

VLSI CIRCUITS;

EID: 0035398674     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.931040     Document Type: Article

References (19)

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