Channel length extraction for DMOS transistors using capacitance-voltage measurements

IEEE Transactions on Electron Devices

Volumn 48, Issue 7, 2001, Pages 1454-1459

  Valtonen, Roger ^a,b   Olsson, Jörgen ^a,b   De Wolf, Peter ^c  

^a IEEE   (Sweden)

^b UPPSALA UNIVERSITY   (Sweden)

^c Digital Instruments   (United States)

Author keywords

Channel length; DMOS transistors; Extraction

Indexed keywords

SCANNING CAPACITANCE MICROSCOPY (SCM);

CAPACITANCE MEASUREMENT; COMPUTER SIMULATION; ELECTRIC POTENTIAL; SEMICONDUCTOR DEVICE STRUCTURES; WSI CIRCUITS;

MOSFET DEVICES;

EID: 0035396644     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.930666     Document Type: Article

References (12)

1. High performance silicon LDMOS technology for 2 GHz RF power amplifier applications
2. Modeling and characterization of an 80 V silicon LDMOSFET for emerging RFIC applications
3. MOSFET channel length: Extraction and interpretation
4. Measuring the effective channel length of MOSFET's
5. A new method to determine effective MOSFET channel length
6. A new method to determine MOSFET channel length
7. A new shift and ratio method for MOSFET channel length extraction
8. Extraction of lateral device parameters and channel doping profile of vertical double-diffused MOS transistors
9. Integration of a novel high-voltage giga-hertz DMOS transistor into a standard CMOS process
10. eff and channel profile in MOSFET's using 2-D carrier profiling techniques
11. Two-dimensional dopant profiling of a 60 nm gate length n-MOSFET using scanning capacitance microscopy