Overcoming the challenges to feedback-directed optimization

Proceedings of the ACM SIGPLAN Workshop on Dynamic and Adaptive Compilation and Optimization, DYNAMO 2000

Volumn , Issue , 2000, Pages 1-11

  Smith, Michael D ^a  

^a HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SOFTWARE ENGINEERING;

EXECUTABLES; EXECUTION ENVIRONMENTS; FEEDBACK DIRECTED OPTIMIZATIONS; HARDWARE AND SOFTWARE; OPTIMIZERS; PROGRAM BEHAVIOR; STATIC OPTIMIZATION; TEMPORAL BEHAVIOR;

INTERACTIVE DEVICES;

EID: 84948461157     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/351397.351408     Document Type: Conference Paper

References (55)

1. S. Adve, et al. "Changing Interaction of Compiler and Architecture," Computer, 30(12):51-58, December 1997.
2. A. Aho, R. Sethi, and J. Ullman. Compilers: Principles, Techniques, and Tools, Addison Wesley, Reading, MA, 1988, p. 589.
3. D. Albonesi. "Dynamic IPC/Clock Rate Optimization," Proc. 25th Annual International Symposium on Computer Architecture, pp. 282-292, June 1998.
4. G. Alpert. "A Transparent Method for Correlating Profiles with Source Programs," Proc. Second Workshop on Feedback-Directed Optimization, held in conjunction with MICRO-33, pp. 33-39, November 1999
5. J. Anderson, et al., "Continuous Profiling: Where Have All the Cycles Gone?," Proc. 16th ACM Symposium on Operating Systems Principles (SOSP), October 1997.
6. P. Andersen. "Partial Evaluation Applied to Ray Tracing," unpublished technical report, January 1995.
7. A. Appel. Modern Compiler Implementation in C, Cambridge University Press, Cambridge, UK, 1998.
8. A. Ayers, S. de Jong, J. Peyton, and R. Schooler. "Scalable Cross-Module Optimization," Proc. A CM SIGPLAN'98 Conference on Programming Language Design and Implementation, pp. 301-312, June 1998.
9. J. Backus. "The History of Fortran I, II, and JJL" IEEE Annuals of the History of Computing, 20(4), Oct.-Dec. 1990.
10. V. Bala, E. Duesterwald, and S. Banerjia. "Dynamo: A Transparent Runtime Optimization System," to appear in the ACM SIGPLAN 2000 Conference on Programming Language Design and Implementation, June 2000.
11. T. Ball and J. Larus, "Efficient Path Profiling," Proc. 29th Annual International Symposium on Microarchitecture, pp. 46-57,1996.
12. M. Burke, et al. "The Jalapefto Dynamic Optimizing Compiler for Java," Proc. ACM Java Grande Conference, June 1999.
13. R. Cohn and G Lowney. "Hot Cold Optimization of Large Windows/NT Applications," Proc. 29th Annual International Symposium on Microarchitecture, pp. 80-89, December 1996.
14. R. Cohn and G Lowney. "Feedback Directed Optimization in Compaq's Compilation Tools for Alpha," Proc. Second Workshop on Feedback-Directed Optimization, held in conjunction with MICRO-33, pp. 3-12, November 1999.
15. C. Consel, et al. "Tempo: Specializing systems applications and beyond," A CM Computing Surveys, Symposium on Partial Evaluation, 30(3), 1998.
16. T. Conte and S. Sathaye, "Dynamic rescheduling: A technique for object code compatibility in VLIW architectures," Proc. 28th Annual International Symposium on Microarchitecture, November 1995.
17. T. M. Conte, K. N. Menezes and M. A. Hirsch, "Accurate and practical profile-driven compilation using the profile buffer," Proc. 29th Annual International Symposium on Microarchitecture, pp. 36-45, December 1996.
18. C. Dulong, et al. "An Overview of the Intel IA-64 Compiler," Intel Technology Journal, November 22,1999 (Q4).
19. K. Ebcioglu and E. Airman. "Dynamic Compilation for 100% Architectural Compatibility," Proc. 24th Annual International Symposium on Computer Architecture, pp. 26-37, June 1997.
20. D. Engler, W. Hsieh, and M. Kaashoek. "'C: A Language for High-Level, Efficient, and Machine-Independent Dynamic Code Generation," Proc. 23rd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, pp. 131-144, January 1996.
21. D. Friendly, S. Patel, and Y. Part. "Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors," Proc. 31st Annual International Symposium on Microarchitecture, pp. 173-181, November 1998.
22. N. Gloy and M. Smith. "Procedure Placement using Temporal-Ordering Information," ACM Transactions on Programming Languages and Systems, 21(5):977-1027, September 1999.
23. B. Grant, et al. "Annotation-Directed Run-Time Specialization in C," Proc. ACM SIGPLAN Symposium on Partial Evaluation and Semantics-Based Program Manipulation, pp. 163-178, June 1997.
24. B. Grant, et al. "An Evaluation of Staged Run-Time Optimizations in DyC," Proc. ACM SIGPLAN1999 Conference on Programming Language Design and Implementation, pp. 293304, May 1999.
25. R. Gupta, D. Berson, and J. Fang. "Path Profile Guided Partial Dead Code Elimination Using Predication," Proc. of Parallel Architectures and Compilation Techniques, pp. 102-115, November 1995.
26. R. Gupta, D. Berson, and J. Fang. 'Tath Profile Guided Partial Redundancy Elimination Using Speculation," Proc. of IEEE International Conference on Computer Languages, pp. 230239, May, 1995.
27. R. Hank, W. Hwu, and B. Rau. "Region-Based Compilation: An Introduction and Motivation," Proc. 28th Annual International Symposium on Microarchitecture, pp. 158-168, November 1995.
28. R. Hookway and M. Herdeg, "DIGITAL FX! 32: Combining Emulation and Binary Translation," Digital Technical Journal, 9(1):3-12,1997.
29. W. Hwu et al., "The Superblock: An Effective Technique for VLIW and Superscalar Compilation," The Journal of Super-computing 7(l/2):229-248, Kluwer Academic Publishers, May 1993. Also see http://www.crhc.uiuc.edu/hnpact.
30. N. Jouppi. "The Non-Uniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance," IEEE Transactions on Computers, 38(12):1645- 1658, December 1989.
31. B. Kernighan and R. Pike. The Practice of Programming, Addison Wesley, Reading, MA, 1999.
32. A. Klaiber. "The Technology Behind the Crusoe Processors," White paper (http://www.transmeta.com/crusoe/download/pdf7crusoetechwp.pdf), Transmeta Corporation, January 2000.
33. D. Lee, P. Crowley, J.L. Baer, T. Anderson, and B. Bershad. "Execution Characteristics of Desktop Applications on Windows NT," Proc. 25th Annual International Symposium on Computer Architecture, pp. 27-38, June 1998.
34. J. Levine. Linkers and Loaders, Morgan Kaufmann Publishers, San Francisco, CA, 2000.
35. M. Lipasti and J. Shen. "Exceeding the Dataflow Limit Via Value Prediction," Proc. 29th International Symposium on Microarchitecture, pp. 226-237, December 1996.
36. P. Lowney, et al. "The Multiflow Trace Scheduling Compiler," The Journal of Supercomputing, 7:51-142, January 1993.
37. M. Mock, M. Berryman, C. Chambers, and S. Eggers. "Calpa: A Tool for Automating Dynamic Compilation," Proc. Second Workshop on Feedback-Directed Optimization, held in conjunction with MICRO-33, pp. 100-109, November 1999.
38. M. Rinard. "Credible Compilation," MTT Laboratory for Computer Science technical report MJT-LCS-TR-776, Cambridge, MA, March 1999.
39. E. Rohou and M. Smith. "Dynamically Managing Processor Temperature and Power," Proc. Second Workshop on Feedback-Directed Optimization, held in conjunction with the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 73-82, November 1999.
40. E. Rotenberg, et al. "Trace Processors," Proc. 30th Annual International Symposium on Microarchitecture, pp. 138-148, December 1997.
41. S. Savari and C. Young. "Comparing and Combining Profiles," Proc. Second Workshop on Feedback-Directed Optimization, held in conjunction with the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 50-62, November 1999.
42. W. Schmidt, et al. "Profile-Directed Restructuring of Operating System Code," IBM Systems Journal, 37(2):270-297, 1998.
43. T. Sherwood and B. Calder. "Time Varying Behavior of Programs," UC San Diego Technical Report CS99-630, August 1999.
44. J. Smith and Q Sohi. "The Microarchitecture of Superscalar Processors," Proceedings of IEEE, 83(12): 1609-1624, December 1995.
45. M. Smith. "Extending SUIF for Machine-dependent Optimizations," Proc. First SUIF Compiler Workshop, Stanford, CA, pp. 14-25, January 1996. Also see http://www.eecs.har-vard.edu/machsuif.
46. A. Sodani and Q Sohi. "Dynamic Instruction Reuse," Proc. 24th International Symposium on Computer Architecture, pp. 194-205, July 1997.
47. Sun Microsystems. "The Java Hotspot Performance Engine Architecture," White paper (http://java.sun.com/products/hotspot/whitepaper.html), Sun Microsystems, April 1999.
48. C. Tice. "Non-Transparent Debugging of Optimized Code," Ph.D. Dissertation, Computer Science Division Tech Report Number UCB/CSD-99-1077, University of California at Berkeley, October 1999.
49. D. Wall. "Predicting Program Behavior Using Real or Estimated Profiles," Proc. SIGPLAN 1991 Conference on Programming Language Design and Implementation, pp. 59-70, June 1991.
50. Z. Wang and N. Rubin. "Evaluating the Importance of User-Specific Profiling," Proc. 2nd USENIX Windows NT Symposium, August 1998.
51. Z. Wang, K. Pierce, and S. McFarling. "BMAT - A Binary Matching Tool," Proc. Second Workshop on Feedback-Directed Optimization, held in conjunction with MICRO-33, pp. 40-49, November 1999.
52. C. Young, "Path-based Compilation," Ph.D. Dissertation, Division of Engineering and Applied Sciences, Harvard University, Cambridge, MA, January 1998.
53. C. Young and M. Smith, "Better Global Scheduling Using Path Profiles," Proc. 31st Annual International Symposium on Microarchitecture, pp. 115-123, December 1998.
54. C. Young and M. Smith. "Static Correlated Branch Prediction," ACM Transactions on Programming Languages and Systems, 21(5): 1028-1075, September 1999.
55. X. Zhang et al., "System Support for Automatic Profiling and Optimization," Proc. 16th ACM Symposium on Operating Systems Principles, 1997.