Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 3, 2001, Pages 450-460

  Jin, Woojin ^b   Eo, Yungseon ^b   Eisenstadt, William R ^a,c   Shim, Jongin ^b  

^a IEEE   (United States)

^b Hanyang University   (South Korea)

^c J Crayton Pruitt Family Department of Biomedical Engineering   (United States)

Author keywords

Crosstalk; Interconnect capacitance; Multilayer; Shielding effect; Signal delay; VLSI interconnects

Indexed keywords

SIGNAL DELAY; VLSI INTERCONNECTS;

CAPACITANCE; COST EFFECTIVENESS; CROSSTALK; INTERCONNECTION NETWORKS; MULTILAYERS; SHIELDING;

VLSI CIRCUITS;

EID: 0035361132     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.929579     Document Type: Article

References (21)

1. International technology roadmap for semiconductors
2. Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocess
3. eff CMOS technology with copper interconnects
4. Clocking design and analysis for a 600-MHz alpha microprocessor
5. Interconnect scaling - The real limiter to high performance ULSI
6. When are transmission-line effects important for on-chip interconnects?
7. Reducing cross-coupling among interconnect wires in deep-submicron datapath design
8. Calculation of coefficients of capacitance of multiconductor transmission lines in the presence of a dielectric interface
9. Analytically determined quasistatic parameters of shielded or open multiconductor microstrip lines
10. Boundary element method macromodels for 2-D hierarchical capacitance extraction
11. An efficient solver for the three-dimensional capacitance of the interconnects in high speed digital circuit by the multiresolution method of moments
12. A novel modeling technique for efficiently computing 3-D capacitances of VLSI multilevel interconnections-BFEM
13. A technique for fast calculation of capacitance matrices of interconnect structures
14. Three-dimensional capacitance computations for VLSI/ULSI interconnections
15. Fast capacitance extraction of general three-dimensional structures
16. Multilevel metal capacitance models for CAD design synthesis systems
17. Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology
18. Modeling and extraction of interconnect capacitance for multilayer VLSI circuits
19. Automatic generation of analytical models for interconnect capacitances