A novel modeling technique for efficiently computing 3-D capacitances of VLSI multilevel interconnections - BFEM

IEEE Transactions on Electron Devices

Volumn 45, Issue 1, 1998, Pages 200-205

  Hou, Hsin Ming ^a   Sheen, Chin Shown ^a   Wu, Ching Yuan ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

3 d capacitance; BFEM; Green's function; Interconnection; VLSI

Indexed keywords

BOUNDARY ELEMENT METHOD; CAPACITANCE MEASUREMENT; ELECTRIC CHARGE; FINITE ELEMENT METHOD; GREEN'S FUNCTION; INTEGRAL EQUATIONS; POLYNOMIALS; SEMICONDUCTOR DEVICE MODELS;

GALERKIN'S PRINCIPLE;

VLSI CIRCUITS;

EID: 0031647282     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.658831     Document Type: Article

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