Bit-line leakage compensation scheme for low-voltage SRAM's

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2000, Pages 70-71

  Agawa, Ken'ichi ^a   Hara, Hiroyuki ^a   Takayanagi, Toshinari ^a   Kuroda, Tadahiro ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; THRESHOLD VOLTAGE; TRANSISTORS;

BIT LINE LEAKAGE CURRENT (BLC) COMPENSATION; STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0033683112     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)