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Volumn , Issue , 1996, Pages 9-13

The effectiveness of IDDQ and high voltage stress for burn-in elimination [CMOS production]

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; FAILURE ANALYSIS;

EID: 84895110189     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IDDQ.1996.557800     Document Type: Conference Paper
Times cited : (38)

References (14)
  • 4
    • 85068207052 scopus 로고
    • Increase fault coverage with iddq testing
    • August 8
    • "Increase Fault Coverage with Iddq Testing", Electronic Design, August 8, 1994.
    • (1994) Electronic Design
  • 5
    • 85068222870 scopus 로고    scopus 로고
    • Bit Current Option manual, Manual number 8099976-06, ADVANTEST
    • Bit Current Option manual, Manual number 8099976-06, ADVANTEST.
  • 6
    • 0029517664 scopus 로고
    • THE final barriers to widespread use of iddq testing
    • John M. Acken, "THE FINAL BARRIERS TO WIDESPREAD USE OF IDDQ TESTING", 1TC, pp. 300,1995
    • (1995) 1TC , pp. 300
    • Acken, J.M.1
  • 7
    • 0029487490 scopus 로고
    • On the effect of issq testing in reducing early failure rate
    • Kenneth M. Wallquist, "On the Effect of ISSQ Testing in Reducing Early Failure Rate", ITC, pp. 910-915, 1995.
    • (1995) ITC , pp. 910-915
    • Wallquist, K.M.1
  • 8
  • 12
    • 0022659379 scopus 로고
    • Reliability consideration of fine pattern ic
    • Nol, Feb.
    • M. Sugimoto, T. Ajiki, "Reliability Consideration of Fine Pattern IC", National Technical report, ppl57, Vol 32, Nol, Feb. 1986.
    • (1986) National Technical Report , vol.32 , pp. l57
    • Sugimoto, M.1    Ajiki, T.2
  • 13
    • 0029489611 scopus 로고
    • IDDQ testing of CMOS opens: An experimental study
    • A. D. Singh, H. Rasheed, and W.W.Weber, "IDDQ Testing of CMOS Opens: An Experimental Study" ITC-95, pp.479-489,1995.
    • (1995) ITC-95 , pp. 479-489
    • Singh, A.D.1    Rasheed, H.2    Weber, W.W.3
  • 14
    • 85068230166 scopus 로고
    • An evaluation of iddq versus conventionaltesting for CMOS sea-of-gate-ic's
    • (in Japanese)
    • K. Sawada and S. Kayano, "An Evaluation of IDDQ Versus ConventionalTesting for CMOS Sea-of-Gate-IC's" Technical Report of IEICE, pp.9-16,1992. (in Japanese)
    • (1992) Technical Report of IEICE , pp. 9-16
    • Sawada, K.1    Kayano, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.