Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2001, Pages 253-258

  De Heyn, V ^a   Groeseneken, G ^a   Keppens, B ^a   Natarajan, M ^a   Vacaresse, L ^a   Gallopyn, G ^a  

^a IMEC   (Belgium)

Author keywords

Base push out; DMOS; ESD; Reliability; Smart power; TCAD

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC BREAKDOWN OF SOLIDS; ELECTRIC DISCHARGES; ELECTRIC NETWORK SYNTHESIS; ELECTROSTATICS; RELIABILITY; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

BASE PUSH OUT; LATERLA BIPOLAR BASE DISTANCE; SMART POWER TECHNOLOGY; SNAPBACK MECHANISM;

MOS CAPACITORS;

EID: 0034995088     PISSN: 00999512     EISSN: None     Source Type: Journal    
DOI: 10.1109/RELPHY.2001.922910     Document Type: Article

References (12)

1. Analysis and compact modeling of lateral DMOS power devices under ESD stress conditions
2. Investigations on double-diffused MOS (DMOS) transistors under ESD zap conditions
3. Wide range control of sustaining voltage of ESD protection elements realized in smart power technology
4. ESD robustness of smart power protection structures evaluated by means of HBM and TLP tests
5. Lateral DMOS design for ESD robustness
6. Device integration for ESD robustness of high voltage power MOSFETs
7. Efficient NPN operation in high voltage NMOSFET for ESD protection
8. Simulation and experimental study of temperature distribution during ESD stress in smart power technology ESD protection structures
9. Analysis and compact modeling of a vertical grounded-base NPN bipolar transistor used as an ESD protection in a smart power technology
10. ESD characterization of IC's-transmission line pulser
11. Pitfalls when correlating TLP, HBM and MM testing