Design of an embedded fully-depleted SOI SRAM

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn , Issue , 2001, Pages 13-18

  Sung, R J ^a   Koob, J C ^a   Brandon, T L ^a   Elliott, D G ^a   Cockburn, B F ^a  

^a UNIVERSITY OF ALBERTA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA PROCESSING; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT; MICROELECTRONIC PROCESSING; SILICON ON INSULATOR TECHNOLOGY;

FLOATING BODY EFFECTS; SENSE AMPLIFIERS;

STATIC RANDOM ACCESS STORAGE;

EID: 0034869586     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. Silicon on insulator technology
2. SRAM bitline circuits on PD SOI: Advantages and concerns
3. A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor
4. Performance of a low power fully-depleted deep submicron SOI technology and its extension to 0.15 μm
5. Design criteria for a fully-depleted 0.1-μm SOI technology
6. Computational RAM: Implementing processors-in-memory with low area and power overhead
7. A new SRAM cell design using 0.35μm CMOS/SIMOX technology
8. Register files and caches
9. Floating body effects in partially depleted SOI CMOS circuits
10. A 0.2-μm, 1.8-V, SOI, 550-MHz, 64-b powerPC microprocessor with copper interconnects
11. Physical modeling needed for reliable SOI circuit design
12. UFSOI model parameter evaluation: Process-based calibration
13. SRAM cache design considerations