Performance of a low power fully-depleted deep submicron SOI technology and its extension to 0.15 μm

IEEE International SOI Conference

Volumn , Issue , 1996, Pages 102-103

  Burns, J A ^a   Keast, C L ^a   Knecht, J M ^a   Kunz, R R ^a   Palmateer, S C ^a   Cann, S ^a   Soares, A ^a   Shaver, D C ^a  

^a MIT LINCOLN LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; OSCILLATORS (ELECTRONIC); PHOTOLITHOGRAPHY; RADIO FREQUENCY AMPLIFIERS;

OPTICAL LITHOGRAPHY;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0030382430     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)