Maximum voltage variation in the power distribution network of VLSI circuits with RLC models

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 376-381

  Bobba, S ^a   Hajj, I N ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC POWER DISTRIBUTION; FREQUENCY DOMAIN ANALYSIS; LAGRANGE MULTIPLIERS; LOGIC GATES; TIME DOMAIN ANALYSIS; WAVEFORM ANALYSIS;

VOLTAGE VARIATIONS;

VLSI CIRCUITS;

EID: 0034863957     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/383082.383186     Document Type: Conference Paper

References (11)

1. Techniques for calculating currents and voltages in VLSI power supply networks
2. Design of an efficient power distribution network for the UltarSPARC-I microprocessor
3. Full-chip verification methods for DSM power distribution systems
4. Design and analysis of power distribution networks in powerPC microprocessor
5. Power supply noise analysis methodology for deep-submicron VLSI chip design
6. Estimation of maximum power supply noise for deep sub-micron designs
7. Modeling of power distribution systems for high-performance microprocessors
8. Estimation of maximum current envelope for power bus analysis and design
9. Simulation and optimization of the power distribution network in VLSI circuits