Embedded system cost optimization via data path width adjustment

IEICE Transactions on Information and Systems

Volumn E80-D, Issue 10, 1997, Pages 974-981

  Shackleford, Barry ^a   Yasuda, Mitsuhiro ^b   Okushi, Etsuko ^c   Koizumi, Hisao ^d   Tomiyama, Hiroyuki ^b   Inoue, Akihiko ^c   Yasuura, Hiroto ^d  

^a HEWLETT PACKARD LABORATORIES   (United States)

^b MITSUBISHI CORPORATION   (Japan)

^c MITSUBISHI ELECTRIC CORPORATION   (Japan)

^d KYUSHU UNIVERSITY   (Japan)

Author keywords

CPU; Embedded systems; Memory; System on chip

Indexed keywords

COMPUTER PERIPHERAL EQUIPMENT; COST EFFECTIVENESS; DATA STORAGE EQUIPMENT; OPTIMIZATION; PRODUCT DESIGN;

COST OPTIMIZATION; DATA PATH WIDTH ADJUSTMENT; EMBEDDED SYSTEMS;

MICROPROCESSOR CHIPS;

EID: 0031248965     PISSN: 09168532     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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