Simulation-based test algorithm generation and port scheduling for multi-port memories

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 301-306

  Wu, C F ^a   Huang, C T ^a   Cheng, K L ^a   Wang, C W ^a   Wu, C W ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; PROGRAM PROCESSORS; SCHEDULING;

MULTI-PORT MEMORIES;

VLSI CIRCUITS;

EID: 0034848382     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/378239.378491     Document Type: Conference Paper

References (10)

1. Testing complex couplings in multiport memories
2. Fault models and tests for two-port memories
3. An efficient test method for embedded multi-port RAM with BIST circuitry
4. Built-in self-test for multi-port RAMs
5. Detection of inter-port faults in multi-port static RAMs
6. Simulation-based test algorithm generation for random access memories
7. Error catch and analysis for semiconductor memories using March tests
8. A programmable BIST core for embedded DRAM
9. RAMSES: A fast memory fault simulator