Yield and reliability effects of interlevel dielectric plasma enhanced deposition induced charging damage

International Symposium on Plasma Process-Induced Damage, P2ID, Proceedings

Volumn , Issue , 2001, Pages 44-47

  Scarpa, A ^a   Van Marwijk, L ^a   Peters, W ^a   Boter, D ^a   Kuper, F G ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC RESISTANCE; ENERGY DISSIPATION; GATES (TRANSISTOR); INTEGRATED CIRCUIT TESTING; RELIABILITY;

INTERLEVEL DIELECTRIC (ILD);

PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION;

EID: 0034833276     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Relation between product yield and plasma process induced damage
2. Charging damage in metal-oxide-metal capacitors
3. CMOS-circuit protection against PPID for yield enhancement
4. Relationship between yield and reliability impact of plasma damage to gate oxide
5. On the mechanism of plasma enhanced dielectric deposition cahrging damage
6. 2 films: Occurrence characterization and reliability assessment methodology
7. Soft breakdown of ultra-thin gate oxide layers
8. Differentiation between electric breakdown and dielectric breakdown in thin silicon oxides