A 99-mm2, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2001, Pages 425-428

  Kumaki, S ^a   Takata, H ^a   Ajioka, Y ^a   Ooishi, T ^a   Ishihara, K ^a   Hanami, A ^a   Tsuji, T ^a   Kanehira, Y ^a   Watanabe, T ^a   Morishima, C ^a   Yoshizawa, T ^a   Sato, H ^a   Hattori, S ^a   Koshio, A ^a   Tsukamoto, K ^a   Matsumura, T ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; HIGH DEFINITION TELEVISION; IMAGE CODING; IMAGE COMPRESSION; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; REAL TIME SYSTEMS; TELEVISION SYSTEMS;

AUDIO ENCODING; SYSTEM ENCODING; VIDEO ENCODING;

LSI CIRCUITS;

EID: 0034827313     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. A 1.5-W single-chip MPEG2 MP@ML encoder with low power motion estimation and clocking
2. A 1.2W single-chip MPEG2 MP@ML video encoder LSI including wide search range motion estimation and 81 MOPS controller
3. 2, 0.95-W, single-chip MPEG2 MP@ML video encoder with a 128 GOPS motion estimator and a multi-tasking RISC-type controller
4. A single-chip MPEG2 MP@ML video encoder LSI with multi-chip configuration for a single board MP@HL encoder
5. High density embedded DRAM technology with 0.38μm pitch in DRAM and 0.42μm pitch in LOGIC by W/PolySi gate and Cu dual damascene metallization
6. An architectural study of an MPEG-2 422P@HL encoder chip set
7. A single-chip MPEG2 422@ML video, audio, and system encoder with a 162MHz media-processor and dual motion estimation cores
8. A 1.0V 230MHz column access embedded DRAM macro with dual interface and triple test functions for portable MPEG applications