An architectural study of an mpeg-2 422p@hl encoder chip set

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E82-A, Issue 8, 2000, Pages 1614-1622

  Harada, Ayako ^a   Hattori, Shin Ichi ^a   Kasezawa, Tadashi ^a   Sato, Hidenori ^a   Matsumura, Tetsuya ^a   Kumaki, Satoshi ^a   Ishihara, Kazuya ^a   Segawa, Hiroshi ^a   Hanami, Atsuo ^a   Matsuura, Yoshinori ^a   Asano, Ken Ichi ^a   Toshiba, Toyohiko ^a   Yoshimoto, Masahiko ^a   Murakami, Tokumichi ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

HDTV; Motion estimation; MPEG 2; Video compression; Video encoder

Indexed keywords

MOTION ESTIMATION; MOVING PICTURE EXPERTS GROUP; VIDEO ENCODER;

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); HIGH DEFINITION TELEVISION; IMAGE COMPRESSION; IMAGE QUALITY; IMAGE RECONSTRUCTION; INTEGRATED CIRCUIT MANUFACTURE; LSI CIRCUITS; MOTION COMPENSATION;

DIGITAL SIGNAL PROCESSING;

EID: 0034247037     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (13)

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