Development of low-cost and highly reliable wafer process package

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2001, Pages 40-46

  Kazama, A ^a   Satoh, T ^a   Yamaguchi, Y ^a   Anjoh, I ^a   Nishimura, A ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; ELASTIC MODULI; FINITE ELEMENT METHOD; RELIABILITY; SOLDERED JOINTS; STRESS RELAXATION; THERMAL CYCLING; TIN ALLOYS;

SOLDER BUMPS; TEMPERATURE CYCLING; UNDERFILL ASSEMBLY; WAFER LEVEL CHIP SCALE PACKAGE;

CHIP SCALE PACKAGES;

EID: 0034822638     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. A wafer level chip size package embedded with a compliant layer
2. Wafer level chip scale packaging (WL-CSP): An overview
3. SuperCSP™
4. Development of real CSP using wafer level assembly process
5. The solder joint and runner metal reliability of wafer-level CSP(Omega-CSP)
6. Fab integrated packaging(FIP): A new concept for high reliability wafer-level chip size packaging
7. Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies
8. Development of a high-volume solder bump formation method
9. Shape prediction of solder bump joint by surface tension analysis and fatigue strength evaluation
10. Fatigue life evaluation of solder ball joints
11. Optimal structure of wafer level package for the electrical performance