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Volumn , Issue , 2001, Pages 41-48

ESD protection device issues for IC designs

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC EQUIPMENT PROTECTION; ELECTRIC RESISTANCE; ELECTROSTATICS; HUMAN FORM MODELS; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; RELIABILITY; THERMAL EFFECTS;

EID: 0034821496     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (15)

References (31)
  • 15
    • 0032316866 scopus 로고    scopus 로고
    • ESD protection for mixed voltage I/O using NMOS transistors stacked in a cascoded configuration
    • (1998) ESD Symp. Proc. , pp. 54-62
    • Anderson, W.1
  • 16
    • 0003615678 scopus 로고
    • ESD protection in a multi-rail disconnected power grid and mixed voltage interface environment in 0.5 and 0.25 um channel length CMOS technologies
    • (1994) ESD Symp. Proc. , pp. 125
    • Voldman, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.