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Volumn 22, Issue 4, 2000, Pages 13-24

On-chip multiprocessor with simultaneous multithreading

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER PROGRAMMING; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; REDUCED INSTRUCTION SET COMPUTING; TRANSISTORS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 0034500318     PISSN: 12256463     EISSN: None     Source Type: Journal    
DOI: 10.4218/etrij.00.0100.0402     Document Type: Article
Times cited : (5)

References (24)
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  • 6
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    • Egger, S.1
  • 8
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    • A single-chip multiprocessor
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  • 9
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    • Arnarashinhe, S.1
  • 10
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    • Agarwal, A.1
  • 15
    • 0026869165 scopus 로고
    • Improved multithreading techniques for hiding communication latency in multiprocessors
    • B. Boothe and A. Ranade. "Improved multithreading techniques for hiding communication latency in multiprocessors," Proc. of Int'l Symp. on Computer Architecture, 1992, pp. 214-223.
    • (1992) Proc. of Int'l Symp. on Computer Architecture , pp. 214-223
    • Boothe, B.1    Ranade, A.2
  • 17
  • 20
    • 0002255264 scopus 로고
    • SPLASH: Stanford parallel applications for shared memory
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  • 22
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    • Dec.
    • Woo-Jong Hahn, Suk-Han Yoon, Kwangwoo Lee, and Michel Dubois, "Evaluation of Cluster-Based System for OLTP Application," ETRI Journal, Vol. 20, No. 4, Dec. 1998, pp. 301-326.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.