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Volumn 44, Issue 12, 2000, Pages 2259-2264

Self-aligned silicon-on-insulator nano flash memory device

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC; DATA STORAGE EQUIPMENT; ELECTRON BEAM LITHOGRAPHY; EMBEDDED SYSTEMS; NANOSTRUCTURED MATERIALS; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; THERMOOXIDATION; THRESHOLD VOLTAGE;

EID: 0034499173     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(00)00221-5     Document Type: Article
Times cited : (24)

References (8)
  • 1
    • 0030399245 scopus 로고    scopus 로고
    • Si single-electron MOS memory with nanoscale floating-gate and narrow channel
    • Guo L, Leobandung E, Chou SY. Si single-electron MOS memory with nanoscale floating-gate and narrow channel. IEDM Tech Dig 1996:955-956.
    • (1996) IEDM Tech Dig , pp. 955-956
    • Guo, L.1    Leobandung, E.2    Chou, S.Y.3
  • 3
    • 0030382660 scopus 로고    scopus 로고
    • Room temperature operation of Si single-electron memory with self-aligned floating dot gate
    • Nakajima A, Futatsugi T, Kosemura K, Fukano T, Yokoyama N. Room temperature operation of Si single-electron memory with self-aligned floating dot gate. IEDM Tech Dig 1996:952-954.
    • (1996) IEDM Tech Dig , pp. 952-954
    • Nakajima, A.1    Futatsugi, T.2    Kosemura, K.3    Fukano, T.4    Yokoyama, N.5
  • 4
    • 0033350529 scopus 로고    scopus 로고
    • Room temperature single electron effects in a Si nano-crystal memory
    • Kim I., Han S., Han K., Lee J., Shin H. Room temperature single electron effects in a Si nano-crystal memory. IEEE Electron Dev Lett. 20(12):1999;630-631.
    • (1999) IEEE Electron Dev Lett , vol.20 , Issue.12 , pp. 630-631
    • Kim, I.1    Han, S.2    Han, K.3    Lee, J.4    Shin, H.5
  • 5
    • 0000062702 scopus 로고    scopus 로고
    • Fabrication of twin nano silicon wires based on arsenic dopant effect
    • Tang X., Baie X., Colinge J.P. Fabrication of twin nano silicon wires based on arsenic dopant effect. Jpn J Appl Phys. 37(3B):1998;1591-1593.
    • (1998) Jpn J Appl Phys , vol.37 , Issue.3 B , pp. 1591-1593
    • Tang, X.1    Baie, X.2    Colinge, J.P.3
  • 7
    • 0001905972 scopus 로고    scopus 로고
    • Fabrication, characterisation and self-consistent simulation of SOI nano flash memory device
    • Tang X, Baie X, Bayot V, Van de Wiele F, Colinge JP. Fabrication, characterisation and self-consistent simulation of SOI nano flash memory device. IEDM Tech Dig 1999:919-921.
    • (1999) IEDM Tech Dig , pp. 919-921
    • Tang, X.1    Baie, X.2    Bayot, V.3    Van De Wiele, F.4    Colinge, J.P.5
  • 8
    • 0018515262 scopus 로고
    • 2 interface oxidation kinetics: A physical model for the influence of high substrate doping levels
    • 2 interface oxidation kinetics: a physical model for the influence of high substrate doping levels. J Electrochem Soc. 126(9):1979;1516-1522.
    • (1979) J Electrochem Soc , vol.126 , Issue.9 , pp. 1516-1522
    • Ho, C.P.1    Plummer, J.D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.