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Volumn 2000-January, Issue , 2000, Pages 491-498

Efficient delay calculation in presence of crosstalk

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; ELECTRIC NETWORK PARAMETERS; TIMING CIRCUITS;

EID: 84950136193     PISSN: 19483287     EISSN: 19483295     Source Type: Journal    
DOI: 10.1109/ISQED.2000.838932     Document Type: Article
Times cited : (18)

References (19)
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  • 4
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    • Proc. DAC 1997 , pp. 46-51
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  • 5
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    • Efficient coupled noise estimation for on-chip interconnects
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    • Proc. ICCAD 1997 , pp. 147-151
    • Devgan, A.1
  • 7
    • 0031704625 scopus 로고    scopus 로고
    • New efficient algorithms for computing effective capacitance
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    • Proc. ISPD 1998 , pp. 147-151
    • Kahng, A.B.1    Muddu, S.2
  • 10
    • 0000682349 scopus 로고
    • A switch-level timing verifier for digital MOS VLSI
    • July
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    • (1985) IEEE Trans. on CAD , pp. 336-349
    • Ousterhout, J.K.1
  • 11
    • 0029510043 scopus 로고    scopus 로고
    • Coping with RC (L) interconnect design headaches
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    • Proc. ICCCD 1995 , pp. 246-253
    • Pillage, L.1
  • 12
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    • Asymptotic waveform evaluation for timing analysis
    • April
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    • (1990) IEEE Transaction on CAD , vol.9 , Issue.4 , pp. 352-366
    • Pillage, L.T.1    Rohrer, R.A.2
  • 14
    • 0028756124 scopus 로고
    • Modeling the "effective capacitance" for the RC interconnect of CMOS gates
    • December
    • J. Qian, S. Pullela, and L. Pillage, "Modeling the "Effective Capacitance" for the RC Interconnect of CMOS Gates", IEEE Trans. on CAD vol. 13, no. 12, December 1994, pp1526-1535.
    • (1994) IEEE Trans. on CAD , vol.13 , Issue.12 , pp. 1526-1535
    • Qian, J.1    Pullela, S.2    Pillage, L.3
  • 15
    • 0020778211 scopus 로고
    • Signal delay in RC tree networks
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    • J. Rubinstein, P. Penfield, "Signal Delay in RC Tree Networks", IEEE Trans. on CAD, vol. cad-2, no. 3, July 1983, pp202-211.
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  • 16
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    • An explicit RC-circuit delay approximation based on the first three moments of the impulse response
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    • Tutuianu, B.1    Dartu, F.2    Pileggi, L.3
  • 19
    • 0031099379 scopus 로고    scopus 로고
    • Crosstalk reduction for VLSI
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    • A. Vittal, M. Marek-Sadowska, "Crosstalk Reduction for VLSI", IEEE Trans. on CAD, March, 1997, vol. 16, no. 3, pp. 290-298.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.