Crosstalk aware static timing analysis: A two step approach

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2000-January, Issue , 2000, Pages 499-503

  Franzini, B ^a   Forzan, C ^a   Pandini, D ^a   Scandolara, P ^a   Dal Fabbro, A ^a  

^a STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN; INTEGRATED CIRCUIT INTERCONNECTS;

COUPLING CAPACITANCE; CROSSTALK EFFECT; DELAY CALCULATION; DESIGN VERIFICATION; INTERCONNECT NETWORKS; STATIC TIMING ANALYSIS; TIMING PERFORMANCE; TWO-STEP APPROACH;

CROSSTALK;

EID: 84950136715     PISSN: 19483287     EISSN: 19483295     Source Type: Journal    
DOI: 10.1109/ISQED.2000.838935     Document Type: Article

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