Cell delay fault testing for iterative logic arrays

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 9, Issue 3, 1996, Pages 311-316

  Lu, Shyue Kung ^a   Wu, Cheng Wen ^b   Hwang, Ruei Zong ^c  

^a Loong Hua Institute of Technology and Commerce   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^c Chung Sun Institute of Science and Technology   (Taiwan)

Author keywords

C testable; Cell delay fault; Iterative logic array; Path delay fault; Pseudoexhaustive testing

Indexed keywords

ARRAYS; FAILURE ANALYSIS; ITERATIVE METHODS; TECHNOLOGY; TESTING; VLSI CIRCUITS;

CELL DELAY FAULT; ITERATIVE LOGIC ARRAY; PATH DELAY FAULT; PSEUDOEXHAUSTIVE TESTING;

LOGIC DEVICES;

EID: 0030387197     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF00134694     Document Type: Article

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