Analytic model of parasitic capacitance attenuation in CMOS devices with hyper-thin oxides

Electronics Letters

Volumn 36, Issue 20, 2000, Pages 1699-1700

  Ahmed, K ^a   Ibok, E ^c   Hauser, J ^b  

^a Mail Stop H011 109 ^*  (United States)

^b North Carolina State University   (United States)

^c NONE

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; SEMICONDUCTOR DEVICE MODELS; SUBSTRATES;

HYPERTHIN OXIDES; PARASITIC CAPACITANCE;

CMOS INTEGRATED CIRCUITS;

EID: 0034274999     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20001160     Document Type: Article

References (11)

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