A 1.2-W single-chip MPEG2 MP@ML video encoder LSI including wide search range (H: ±288, V: ±96) motion estimation and 81-MOPS controller

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 11, 1998, Pages 1765-1771

  Ogura, Eiji ^a,b,c   Takashima, Masatoshi ^a,d,e   Hiranaka, Daisuke ^a,f   Ishikawa, Toshiro ^a,g,h,i   Yanagita, Yukio ^a,j   Suzuki, Shuji ^a,k   Fukuda, Tokuya ^a,i,l   Ishii, Toshiyuki ^a,e,m  

^a SONY CORPORATION   (Japan)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^d TOKYO CITY UNIVERSITY   (Japan)

^e Media Processing Laboratories   (Japan)

^f OSAKA UNIVERSITY   (Japan)

^g KAGOSHIMA UNIVERSITY   (Japan)

^h NTT CORPORATION   (Japan)

ⁱ Semiconductor Company   (Japan)

^j UNIVERSITY OF TOKYO   (Japan)

^k RIKKYO UNIVERSITY   (Japan)

^l KEIO UNIVERSITY   (Japan)

^m WASEDA UNIVERSITY   (Japan)

more..

Author keywords

Large scale integration; Motion compensation; Video signal processing

Indexed keywords

ADAPTIVE ALGORITHMS; COMPUTATIONAL COMPLEXITY; ELECTRIC NETWORK ANALYSIS; IMAGE ANALYSIS; IMAGE CODING; IMAGE QUALITY; MICROPROCESSOR CHIPS; MOTION COMPENSATION; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; STANDARDS; VIDEO SIGNAL PROCESSING;

MOTION ESTIMATION; MOTION PICTURE EXPERTS GROUP (MPEG) STANDARDS;

LSI CIRCUITS;

EID: 0032202538     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.726574     Document Type: Article

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