Adaptive digital correction of analog errors in MASH ADC's-part II: Correction using test-signal injection

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 47, Issue 7, 2000, Pages 629-638

  Kiss, Péter ^a   Silva, José ^a   Wiesbauer, Andreas ^a   Sun, Tao ^a   Moon, Un Ku ^a  

^a Oregon State University   (United States)

Author keywords

ADC; Delta sigma; Digital correction; MASH; On line adaptive compensation; Sigma delta; Test signal

Indexed keywords

DIGITAL FILTERS; ERROR COMPENSATION; RANDOM PROCESSES; SIGNAL FILTERING AND PREDICTION; SPURIOUS SIGNAL NOISE;

ADAPTIVE DIGITAL CORRECTION; TEST-SIGNAL INJECTION;

DELTA SIGMA MODULATION;

EID: 0034225770     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.850422     Document Type: Article

References (23)

1. G. Cauwenberghs and G. C. Ternes, "Adaptive digital correction of analog errors in MASH ADCs-Part I: Off-line and blind on-line calibration," IEEE Trans. Circuits Syst. II, pp. 621-628, this issue.
2. A. Marques, V. Peluso, M. S. Steyaert, and W. M. Sansen, "Optimal parameters for delta-sigma modulator topologies," IEEE Trans. Circuits Syst. II, vol. 45, pp. 1232-1241, Sept. 1998.
3. Y. Geerts, A. M. Marques, M. S. J. Steyaert, and W. Sansen, "A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications," IEEE J. Solid-State Circuits, vol. 34, pp. 927-936, July 1999.
4. F. Medeiro, B. P. Verdu, and A. R. Vazquez, "A 13-bit, 2.2-MS/s, 55-mW multibit cascade delta-sigma modulator in CMOS 0.7-ftm single-poly technology," IEEE J. Solid-State Circuits, vol. 34, pp. 748-760, June 1999.
5. T. L. Brooks, D. H. Robertson, D. F. Kelly, A. D. Muro, and S. W. Hartson, "A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR," IEEE J. Solid-State Circuits, vol. 32, pp. 1896-1906, Dec. 1997.
6. G. Cauwenberghs and G. C. Ternes, "Adaptive calibration of multiple quantization oversampled A/D converters," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 1, June 1996, pp. 512-515.
7. S. Abdennadher, S. Kiaei, G. C. Temes, and R. Schreier, "Adaptive selfcalibrating delta-sigma modulators," Electron. Lett., vol. 28, no. 14, pp. 1288-1289, July 1992.
8. Y. Yang, R. Schreier, G. C. Temes, and S. Kiaei, "On-line adaptive digital correction of dual-quantization delta-sigma modulators," Electron. Lett., vol. 28, no. 16, pp. 1511-1513, July 1992.
9. A. Wiesbauer and G. C. Ternes, "Adaptive compensation of analog circuit imperfections for cascaded sigma-delta modulators," in Proc. Asilomar Conf. Circuits, Systems and Computers, vol. 2, Nov. 1996, pp. 1073-1077.
10. -, "Adaptive digital leakage compensation for MASH delta-sigma ADC's," Department of Electrical and Computer Engineering, Oregon State University, Corvallis, OR, July 1997.
11. T. Sun, A. Wiesbauer, and G. C. Temes, "Adaptive compensation of analog circuit imperfections for cascaded delta-sigma ADCs," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 1, June 1998, pp. 405-107.
12. T. Sun, "Compensation Techniques for Cascaded Delta-Sigma A/D Converters and High-Performance Switched-Capacitor Circuits," Ph.D. dissertation, Dept. Elect. Comput. Eng., Oregon State Univ., Corvallis, OR, Sept. 1998.
13. P. Kiss, J. Suva, J. T. Stonick, U. K. Moon, and G. C. Temes, "Improved adaptive digital compensation for cascaded delta-sigma ADCs," in Proc. IEEE Int. Symp. Circuits and Systems, May 2000, vol. 1, pp. II.33-II.36.
14. G. A. Clark, S. K. Mitra, and S. R. Parker, "Block implementation of adaptive digital filters," IEEE Trans. Circuits Syst., vol. CAS-28, pp. 584-592,June 1981.
15. S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation. Piscataway, NJ: IEEE Press, 1996.
16. T. C. Leslie and B. Singh, "An improved sigma-delta modulator architecture," in Proc. IEEE Int. Symp. Circuits and Systems, May 1990, pp. 372-375.
17. J. J. Paulos, G. T. Brauns, M. B. Steer, and S. H. Ardalan, "Improved signal-to-noise ratio using tri-level delta-sigma modulation," in Proc. IEEE Int. Symp. Circuits and Systems, May 1987, pp. 463-166.
18. S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, "A 10-b 20-Msample/s analog-to-digital converter," IEEEJ. Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992.
19. J. Steensgaard-Madsen, "High-Performance Data Converters," Ph.D. dissertation, Dept. Info. Technol., Tech. Univ. of Denmark, , Denmark, Mar. 1999.
20. W. Qin, B. Hu, and X. Ling, "Sigma-delta ADC with reduced sample rate multibit quantizer," IEEE Trans. Circuits Syst. II, vol. 46, pp. 824-828, June 1999.
21. A. Panigada, "14-bit 20-MS/s 4x oversampled cascaded delta-sigmapipelined A/D converter for broad-band communications," M.S. thesis (in Italian), Univ. Pavia, Facultâ di Ingegneria, Pavia, Italy, July 1999.
22. U. K. Moon, J. Suva, J. Steensgaard, and G. C. Temes, "A switchedcapacitor DAC with analog mismatch correction," Electron. Lett., vol. 35, no. 22, pp. 1903-1904, Oct. 1999.
23. M. Sarhang-Nejad and G. C. Temes, "A high-resolution multibit sigmadelta ADC with digital correction and relaxed amplifier requirements," IEEEJ. Solid-State Circuits, vol. 28, pp. 648-660, June 1993.