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Volumn 46, Issue 6, 1999, Pages 824-828

Sigma-delta ADC with reduced sample rate multibit quantizer

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELTA SIGMA MODULATION; DIGITAL FILTERS; MATHEMATICAL MODELS; SAMPLING; SPURIOUS SIGNAL NOISE; TRANSFER FUNCTIONS;

EID: 0033148430     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.769792     Document Type: Article
Times cited : (18)

References (11)
  • 4
    • 33847126300 scopus 로고    scopus 로고
    • 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping," IEEE J. Solid-State Circuits, vol. 22, pp. 921-929, Dec. 1987
    • Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, and T. Yoshitome, "A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping," IEEE J. Solid-State Circuits, vol. 22, pp. 921-929, Dec. 1987.
    • K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, and T. Yoshitome, "A
    • Matsuya, Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.