Incorporating yield enhancement into the floorplanning process

IEEE Transactions on Computers

Volumn 49, Issue 6, 2000, Pages 532-541

  Koren, Israel ^a,b   Koren, Zahava ^b  

^a IEEE   (United States)

^b University of Massachusetts   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLOORPLANNING;

COMPUTATIONAL COMPLEXITY; MICROPROCESSOR CHIPS; REDUNDANCY;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034205833     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.862213     Document Type: Article

References (17)

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