Yield and routing objectives in floorplanning

Proceedings - 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1998

Volumn 1998-December, Issue , 1998, Pages 28-36

  Koren, I ^a   Koren, Z ^a  

^a University of Massachusetts   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; VLSI CIRCUITS;

FLOOR-PLANNING; FLOORPLANS; ROUTING COSTS; TOTAL CHIP AREA; TRADE-OFF ANALYSIS; YIELD ENHANCEMENT;

FAULT TOLERANCE;

EID: 0013005518     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1998.732148     Document Type: Conference Paper

References (11)

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3. G. Evans, "Overview of Techniques for Solving Multiobjective Mathematical Programs, " Management Science, Vol. 30, No. 11, pp 1268-1282, November 1984.
4. T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout, John Wi-ley & Sons, West Essex, England, 1990.
5. Z. Koren and I. Koren, \Does the Floorplan of a Chip Aect Its Yield?" Proc. of the 1993 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 159-166, October 1993.
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9. S. Wimer and I. Koren, \Analysis of Strategies for Constructive General Block Placement, " IEEE Trans. on Computer-Aided Design, Vol. 7, pp. 371-377, March 1988.
10. S. Wimer, I. Koren and I. Cederbaum, \Optimal Aspect Ratios of Building Blocks in VLSI, " IEEE Trans. on Computer-Aided Design, Vol. 8, pp. 139-145, Feb. 1989.
11. S. Wimer, I. Koren and I. Cederbaum, \Optimal Determination of Block Di-mensions in General Floorplans, " Routing, Placement and Partitioning, G.W. Zobrist (ed.), Ch. 7, pp. 237-286, Ablex Publishing Corp., 1994.