Test-set embedding based on width compression for mixed-mode BIST

IEEE Transactions on Instrumentation and Measurement

Volumn 49, Issue 3, 2000, Pages 671-678

  Chakrabarty, Krishnendu ^a,b   Das, Sunil R ^a,c  

^a IEEE   (United States)

^b Duke University   (United States)

^c UNIVERSITY OF OTTAWA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT COVERAGE; PRECOMPUTED TEST SET; TEST GENERATOR CIRCUIT; TESTING TIME;

BUILT-IN SELF TEST; COMBINATORIAL CIRCUITS; FAILURE ANALYSIS; LOGIC DESIGN; SEQUENTIAL CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 0034205606     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/19.850413     Document Type: Article

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