Improved immunity to plasma damage in ultrathin nitrided oxides

IEEE Electron Device Letters

Volumn 21, Issue 1, 2000, Pages 15-17

  Chen, Chi Chun ^a   Lin, Horng Chih ^b   Chang, Chun Yen ^a   Liang, Mong Song ^c   Chien, Chao Hsin ^a   Hsien, Szu Kang ^a   Huang, Tiao Yuan ^a,b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

^c TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC BREAKDOWN OF SOLIDS; ELECTRIC CURRENT MEASUREMENT; GATES (TRANSISTOR); LEAKAGE CURRENTS; NITROGEN OXIDES; SEMICONDUCTING BORON; SEMICONDUCTOR PLASMAS;

ULTRATHIN NITRIDED OXIDES;

ULSI CIRCUITS;

EID: 0033908203     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.817438     Document Type: Article

References (16)

1. D. Crook, M. Domnitei, M. Webb, and J. Bonini, "Evaluation of modern gate oxide technologies to process charging," in Prot: IEEE/IRPS, 1993, p. 255.
2. 2 gate dielectrics," in Proc. IEEE/IRPS, 1995, p. 156.
3. B. W. Min, M. Bhat, L. K. Man, T. H. Cho, A. B. Joshi, R. Mann, L. Chung, and D. L. Kwong, "Impact of process-induced damage on MOSFET reliability and suppression of damage by the use of NO-based oxynitride gate dielectrics," in Int. Symp. VLSI TSA, 1995, p. 273.
4. 2O-grown gate oxides and its impact on threshold voltage variation," IEEE Trans. Electron Devices, vol. 43, p. 982, June 1996.
5. H. Fang, K. S. Krisch, B. J. Gross, C. G. Sodini, J. Chung, and D. A. Antoniadis, "Low-temperature furnace-grown reoxidized nitrided oxide gate dielectric as a barrier to boron penetration," IEEE Electron Device Lett., vol. 13, p. 217, Apr. 1992.
6. 2O aneal," IEEE Electron Device Lett., vol. 15, p. 109, Mar. 1994.
7. K. F. Schuegraf, C. C. King, and C. Hu, "Ultra-thin silicon dioxide leakage current and scaling limit," in Symp. VLSI Technol. Dig. Tech., 1992, p. 18.
8. C. H. Chien, C. Y. Chang, H. C. Lin, T. F. Chang, S. G. Chiou, L. P. Chen, and T. Y. Huang, "Resist-related damage on ultra-thin gate oxide during ashing," IEEE Electron Device Lett., vol. 18, p. 33, 1997.
9. H. C. Lin, C. C. Chen, M. F. Wang, C. H. Chien, S. K. Hsien, T. S. Chao, T. Y. Huang, and C. Y. Chang, "Evaluation of plasma charging damage in ultrathin gate oxides," IEEE Electron Device Lett., vol. 19, p. 68, 1998.
10. H. C. Lin, M. F. Wang, C. C. Chen, S. K. Hsien, C. H. Chien, T. Y. Huang, C. Y. Chang, and T. S. Chao, "Characterization of plasma charging damage in ultrathin gate oxides," in Proc. IEEE/IRPS, 1998, p. 312.
11. J. Shideler, S. Reno, R. Bammi, C. Messick, A. Cowley, and W. Lukaszek, "A new technique for solving wafer charging problems," Semicond. Int., p. 153, July 1995.
12. H. C. Lin, C. H. Chien, and T. Y. Huang, "Characterization of antenna effect by nondestructive gate current measurement," Jpn. J. Appl. Phys., vol. 35, p. L1044, 1996.
13. 2," in IEDM Tech. Dig., 1994, p. 617.
14. J. D. Bude, B. E. Weir, and P. J. Silverman, "Explanation of stress-induced damage in thin oxides," in IEDM Tech. Dig., 1998, p. 179.
15. Y. Shi, T. P. Ma, S. Prasad, and S. Dhanda, "Polarity-dependent tunneling current and oxide breakdown in dual-gate CMOSFET's," IEEE Electron Device Lett., vol. 19, p. 391, 1998.
16. E. Hasegawa, M. Kawata, K. Ando, M. Makabe, M. Kitakata, A. Ishitani, L. Manchanda, M. L. Green, K. S. Krisch, and L. C. Feldman, "The impact of nitrogen profile engineering on ultra-thin nitrided oxide films for dual-gate CMOS ULSI," in IEDM Tech. Dig., 1995, p. 327.