The power consumption of CMOS adders and multipliers

Low-Power CMOS Design

Volumn , Issue , 1998, Pages 218-224

  Swartzlander, Earl E ^b  

^a HEWLETT PACKARD ENTERPRISE   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0343923361     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1109/9780470545058.sect7     Document Type: Chapter

References (13)

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2. T. K. Callaway and J. E. E. Swartzlander, “Estimating the power consumption of CMOS adders,” Proceedings of the 11th Symposium on Computer Arithmetic, 1993, pp. 210-216.
3. T. K. Callaway and E. E. Swartzlander Jr., “Optimizing multipliers for WSI,” IEEE International Conference on Wafer Scale Integration, 1993, pp. 85-94.
4. C. Nagendra, R. M. Owens, and M. J. Irwin, “Power-delay characteristics of CMOS adders,” IEEE Transactions on VLSI Systems, voi. 2, 1994, pp. 377-381.
5. D. Goldberg, “Computer arithmetic,” Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, 1990, pp. A2, A3, A31-A39.
6. S. Turrini, “Optimal group distribution in carry-skip adders,” Proceedings of the 9th Symposium on Computer Arithmetic, Sep. 1989, pp. 96-103.
7. O. L. MacSorley, “High-speed arithmetic in binary computers,” IRE Proceedings, vol. 49, 1961, pp. 67-91.
8. O. J. Bedrij, “Carry-select adder,” IRE Transactions on Electronic Computers, vol. EC-11, Jun. 1962, pp. 340-346.
9. J. Sklansky, “Conditional-sum addition logic,” IRE Transactions on Electronic Computers, vol. EC-9, 1960, pp. 226-231.
10. T. K. Callaway, Area, Delay, and Power Modeling of CMOS Adders and Multipliers. Ph.D. thesis, The University of Texas at Austin, 1996.
11. A. D. Pezaris, “A 40ns 17-bit by 17-bit array multiplier,” IEEE Transactions on Computers, vol. C-20, 1971, pp. 442-447.
12. J. Iwamura, K. Suganuma, M. Kimura, and S. Taguchi, “A CMOS/SOS multiplier,” Proceedings of the ISSCC, 1984, pp. 92-93.
13. C. S. Wallace, “A suggestion for a fast multiplier,” IEEE Transactions on Electronic Computers, vol. EC-13, 1964, pp. 14-17.