Performance driven floorplanning for FPGA based designs

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 1997, Pages 112-118

  Shi, Jianzhong ^a   Bhatia, Dinesh ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; LOGIC CIRCUITS; LOGIC GATES; MACROS; PERFORMANCE; VLSI CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FLOORPLANNING; MACRO CELL MAPPING;

PARALLEL PROCESSING SYSTEMS;

EID: 0030683416     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/258305.258321     Document Type: Conference Paper

References (13)