Synthesis and floorplanning for large hierarchical FPGAs

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 1997, Pages 105-111

  Krupnova, H ^a   Rabedaoro, C ^a   Saucier, G ^a  

^a GRENOBLE INSTITUTE OF TECHNOLOGY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUITS; LOGIC CIRCUITS; LOGIC DESIGN; LOGIC GATES; MACROS; OPTIMIZATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FLOORPLANNING METHOD;

PARALLEL PROCESSING SYSTEMS;

EID: 0030671955     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/258305.258320     Document Type: Conference Paper

References (6)