Double Edge-Triggered D-Flip-Flops for High-Speed CMOS Circuits

IEEE Journal of Solid-State Circuits

Volumn 26, Issue 8, 1991, Pages 1168-1170

  Afghahi, M ^a   Yuan, J ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS, TRIGGER; INTEGRATED CIRCUITS, CMOS;

D FLIP-FLOPS; EDGE-TRIGGERED FLIP-FLOPS;

ELECTRONIC CIRCUITS, FLIP FLOP;

EID: 0026207089     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.90071     Document Type: Article

References (6)

1. S. H. Unger and C. Tan, “Clocking schemes for high-speed digital systems,” IEEE Trans. Comput., vol. C-35, pp. 880–895, 1986.
2. M. Afghahi and C. Svensson, “A unified single phase clocking scheme for VLSI systems,” IEEE J. Solid-State Circuits, vol. 24, pp. 62–71, 1989.
3. M. Afghahi and C. Svensson, “A scalable VLSI synchronous system,” in Proc. IEEE Symp. Circuits Syst. (Finland), 1988, pp. 471–474.
4. S. H. Unger, “Double edge-triggered flip-flops,” IEEE Trans. Comput., vol. C-30, no. 6, pp. 447–451, June 1981.
5. S. Lu and M. Ercegovac, “A novel CMOS implementation of double edge-triggered flip-flops,” IEEE J. Solid-State Circuits, vol. 25, pp. 1008–1010, 1990.
6. Y. Ji-ren and C. Svensson, “High speed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. 24, pp. 62–71, 1989.