An Architectural Approach for Increasing Clock Frequency and Communication Speed In Monolithic Wsi Systems

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 17, Issue 3, 1994, Pages 362-368

  Savaria, Y ^b  

^a UNIVERSITÉ DU QUÉBEC À CHICOUTIMI   (Canada)

^b ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA COMMUNICATION SYSTEMS; ELECTRIC CLOCKS; ELECTRIC DELAY LINES; ELECTRIC INVERTERS; ELECTRIC NETWORK ANALYSIS; PIPELINE PROCESSING SYSTEMS; TELECOMMUNICATION NETWORKS; USER INTERFACES; VLSI CIRCUITS;

CLOCK FREQUENCY; PIPELINE CLOCKING;

WSI CIRCUITS;

EID: 0028483186     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.311785     Document Type: Article

References (10)

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