Design of 25-nm SALVO PMOS devices

IEEE Electron Device Letters

Volumn 21, Issue 5, 2000, Pages 248-250

  Vuong, H H ^a   Chang, C P ^a   Pai, C S ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRODES; GATES (TRANSISTOR); MOS DEVICES; PHOTOLITHOGRAPHY; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS;

METAL GATE ELECTRODES; POLYMETAL GATE ELECTRODES; SELF ALIGNED TECHNOLOGY;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033731340     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.841311     Document Type: Article

References (8)

1. Y. Taur, C. H. Wann, and D. J. Frank, "25 nm CMOS design consideration," in IEDM Tech. Dig., 1998, pp. 789-792.
2. Y. Taur and E. J. Nowak, "CMOS devices below 0.1μm: How high will performance go?," in IEDM Tech. Dig., 1997, pp. 215-218.
3. M. R. Pinto et al., "Three-dimensional characterization of bipolar transistors in a submicron BiCMOS technology using integrated process and device simulation," in IEDM Tech. Dig., 1992, pp. 923-926.
4. C. S. Rafferty et al., "Explanation of reverse short channel effect by defect gradient," in IEDM Tech. Dig., 1993, pp. 311-314.
5. A. Chatterjee et al., "CMOS metal replacement gate transistors using tantalum pentoxide gate insulator," in IEDM Tech. Dig., 1998, pp. 777-780.
6. F. M. Houlihan et al., "193 nm single-layer photoresists based on alternating copolymers of cycloolefins: The use of photogenerators of sulfamic acids," in Proc. SPIE - Advances in Resist Technology and Processing XV, vol. 3333, 1998, pp. 73-81.
7. T. Ohguro et al., " 0.25μm CoSi2 salicide CMOS technology thermally stable up to 1000 °C with high TDDB reliability," in VLSI Symp., 1997, pp. 101-102.
8. A. Ghetti et al., "Self-consistent simulation of quantization effects and tunneling current in ultra-thin gate oxide MOS devices," in Proc. SISPAD, 1999, pp. 239-242.